Verilator
| Use attributes for filter ! | |
| Written in | C++ |
|---|---|
| Operating system | Linux |
| FreeBSD | |
| Microsoft Windows | |
| Cygwin | |
| License | GNU Lesser General Public License |
| Stable release | March 2020 |
| Developers | Wilson Snyder |
| Date of Reg. | |
| Date of Upd. | |
| ID | 2972314 |
About Verilator
Verilator is a free and open-source software tool which converts Verilog to a cycle-accurate behavioral model in C++ or SystemC. It is restricted to modeling the synthesizable subset of Verilog and the generated models are cycle-accurate, 2-state, with synthesis semantics.