ARM Cortex-A55
| Use attributes for filter ! | |
| Microarchitecture | ARMv8. 2-A |
|---|---|
| Predecessor | ARM Cortex-A53 |
| Designed by | Arm Holdings |
| Cores | 1–8 per cluster, multiple clusters |
| L2 cache | 64–256 KB |
| L3 cache | 512 KB – 4 MB |
| Date of Reg. | |
| Date of Upd. | |
| ID | 2344714 |
About ARM Cortex-A55
The ARM Cortex-A55 is a microarchitecture implementing the ARMv8. 2-A 64-bit instruction set designed by ARM Holdings' Cambridge design centre. The Cortex-A55 is a 2-wide decode in-order superscalar pipeline.
ARM Cortex-A55 Photos
